cachanova/synth-explorer
Compiler Explorer for RTL: synthesize Verilog with Yosys and explore timing paths, logic depth, and fanin/fanout interactively
TypeScript
Stars
36
Forks
1
License
Apache-2.0
Open Issues
2
Updated
1h ago
No README available
Statistics
- Stars
- 36
- Forks
- 1
- Open Issues
- 2
- Created
- Jul 10, 2026
- Updated
- Jul 22, 2026